Communication systems employing techniques for bit synchronization must trade off hardware complexity for accuracy of synchronization. The most important parameter affecting the type of hardware needed is the noise coupled into the incoming data stream. Noise which manifests itself as duty cycle variations in the data stream can be handled with various techniques. When the signal-to-noise ratio is low, techniques are typically employed which recover an "average" frequency over many data transitions. The lower the signal-to-noise ratio, the more data transitions must be included in the averaging process to accurately recover data, which complicates the hardware.
In strong signal conditions it is possible to accurately recover data using a single transition period for synchronization (assumes prior knowledge of the bit rate). Digital circuits using this method for bit synchronization utilize a clock which is a substantial multiple of the transition rate (usually no less than six times) to allow for synchronization with respect to the modulation transitions. As the data rate increases it becomes more difficult to operate the digital circuitry at this multiplier of the data rate. Analog techniques are typically employed when the data transition rate is significantly higher than 25 Mbit/s.
In communication systems where size and cost are significant production and utilization control factors, the use of separate or auxiliary signal processing networks may not be either practical or even realizable. In a digital CMOS system, for example, the translation of a communication system design into a semiconductor (e.g. silicon) chip mandates a maximum utilization of the resources of the wafer and avoidance of hybrid or off-chip components, making the above-referenced clock/data recovery mechanisms unattractive from both a production and a cost standpoint.